Title :
Extremely-low-noise CMOS Image Sensor with high saturation capacity
Author :
Itonaga, K. ; Mizuta, K. ; Kataoka, T. ; Yanagita, M. ; Ikeda, H. ; Ishiwata, H. ; Tanaka, Y. ; Wakano, T. ; Matoba, Y. ; Oishi, T. ; Yamamoto, R. ; Arakawa, S. ; Komachi, J. ; Katsumata, M. ; Watanabe, S. ; Saito, S. ; Haruta, T. ; Matsumoto, S. ; Ohno,
Author_Institution :
Semicond. Technol. Dev. Div., Sony Corp., Tokyo, Japan
Abstract :
We have developed a flat device structure, which we call “FLAT”, with no isolation grooves/ridges and no Si substrate etching in the imaging area of the CMOS Image Sensor (CIS). We employed this FLAT structure to achieve a 1.12 μm pitch pixel CIS with a 1.25 transistor/pixel architecture and excellent image quality. It uses FLAT transistors(Trs) that generate greatly-reduced 1/f noise, and FLAT isolators (Isos) that increase the saturation capacity (Qs) due to increasing both effective photodiode (PD) area and PD potential under low dark current.
Keywords :
1/f noise; CMOS image sensors; MOSFET; photodiodes; 1/f noise; FLAT isolators; FLAT transistors; effective photodiode area; flat device structure; high saturation capacity; image quality; isolation grooves-ridges; low dark current; low-noise CMOS image sensor; pitch pixel CIS; substrate etching; transistor-pixel architecture; Dark current; Layout; Logic gates; Noise; Silicon; Thermal noise; Transistors;
Conference_Titel :
Electron Devices Meeting (IEDM), 2011 IEEE International
Conference_Location :
Washington, DC
Print_ISBN :
978-1-4577-0506-9
Electronic_ISBN :
0163-1918
DOI :
10.1109/IEDM.2011.6131511
