Title :
A middle-1X nm NAND flash memory cell (M1X-NAND) with highly manufacturable integration technologies
Author :
Hwang, Joowon ; Seo, Jihyun ; Lee, Youngbok ; Park, Sungkee ; Leem, Jongsoon ; Kim, Jaeseok ; Hong, Tackseung ; Jeong, Seokho ; Lee, Kyeongbock ; Heo, Hyeeun ; Lee, Heeyoul ; Jang, Philsoon ; Park, Kyounghwan ; Lee, Myungshik ; Baik, Seunghwan ; Jumsoo Ki
Author_Institution :
Flash Device Dev. & Adv. Process Team, Hynix Semicond. Inc., Icheon, South Korea
Abstract :
A middle-1x nm design rule multi-level NAND flash memory cell (M1X-NAND) has been successfully developed for the first time. 1) QSPT (Quad Spacer Patterning Technology) of ArF immersion lithography is used for patterning mid-1x nm rule wordline (WL). In order to achieve high performance and reliability, several integration technologies are adopted, such as 2) advanced WL air-gap process, 3) floating gate slimming process, and 4) optimized junction formation scheme. And also, by using 5) new N±1 WL Vpass scheme during programming, charge loss and program speed are greatly improved. As a result, mid-1x nm design rule NAND flash memories has been successfully realized.
Keywords :
circuit optimisation; flash memories; immersion lithography; integrated circuit interconnections; integrated circuit layout; integrated circuit reliability; nanoelectronics; nanopatterning; M1X-NAND; QSPT; WL air-gap process; charge loss; floating gate slimming process; immersion lithography; mid-1x nm rule wordline patterning; middle-1x nm design rule multilevel NAND flash memory cell; optimized junction formation scheme; program speed; quad spacer patterning technology; Air gaps; Couplings; Electric fields; Flash memory; Interference; Junctions; Logic gates;
Conference_Titel :
Electron Devices Meeting (IEDM), 2011 IEEE International
Conference_Location :
Washington, DC
Print_ISBN :
978-1-4577-0506-9
Electronic_ISBN :
0163-1918
DOI :
10.1109/IEDM.2011.6131518
