Scaling feasibility study of planar thin floating gate (FG) NAND Flash devices and size effect challenges beyond 20nm

Scaling of the planar thin FG NAND device down to 20nm is experimentally studied for the first time. Using a thin FG (<;10nm) and a barrier engineered CT IPD the 20nm device showed reasonable memory window and endurance, but the overall memory window is significantly degraded compared to longer channel devices. Through detailed 3D TCAD simulations we find that the edge fringing field plays the dominant role in the memory window degradation. The conventional short-channel Vt roll-off effect also induces a significant programmed-state subthreshold slope (S.S.) degradation that also reduces the memory window. Control gate height and several device parameters are discussed in order to provide an overview of size effect on the scaling of planar thin FG NAND devices.