Title :
Scalability of split-gate charge trap memories down to 20nm for low-power embedded memories
Author :
Masoero, L. ; Molas, G. ; Brun, Francesco ; Gely, M. ; Colonna, J.P. ; Della Marca, V. ; Cueto, O. ; Nowak, E. ; De Luca, A. ; Brianceau, P. ; Charpin, C. ; Kies, R. ; Toffoli, A. ; Lafond, D. ; Delaye, V. ; Aussenac, F. ; Carabasse, C. ; Pauliac, Sebasti
Author_Institution :
Leti, CEA, Grenoble, France
Abstract :
In this work, split-gate charge trap memories with electrical gate length down to 20 nm are presented for the 1st time. Silicon nanocristals (Si-ncs), or silicon nitride (Si3N4) and hybrid Sinc/SiN based split-gate memories, with SiO2 or Al2O3 control dielectrics, are compared in terms of program erase and retention. Then, the scalability of split-gate charge trap memories is studied, investigating the impact of gate length reduction on the memory window, retention and consumption. The results are analyzed by means of TCAD simulations.
Keywords :
aluminium compounds; elemental semiconductors; embedded systems; flash memories; nanostructured materials; silicon; silicon compounds; technology CAD (electronics); Si-Si3N4-Al2O3; Si-Si3N4-SiO2; TCAD simulation; electrical gate length; hybrid Si-nanocrystal-SiN based split-gate memory; low-power embedded memory; memory window; silicon nanocrystal; silicon nitride; size 20 nm; split-gate charge trap memory; Charge carrier processes; Dielectrics; Electric fields; Logic gates; Programming; Silicon compounds; Split gate flash memory cells;
Conference_Titel :
Electron Devices Meeting (IEDM), 2011 IEEE International
Conference_Location :
Washington, DC
Print_ISBN :
978-1-4577-0506-9
Electronic_ISBN :
0163-1918
DOI :
10.1109/IEDM.2011.6131522
