Volumetric Degenerative Routing for 3D Network-on-chip

As we reach the limits of scaling down of circuits, Three Dimensional Integrated Circuits (3D ICs) offer a very promising opportunity to keep on increasing the processing capacities and speed. In a Multi-Processor System-on-Chip (MPSoC) based embedded system with Network-on-chip (NOC) as the communication architecture [1], routing of the traffic among the Processing Elements (PEs) contributes significantly to the global latency, throughput and energy consumption. Almost all prior studies have focused on 2D NOC designs. The field of 3D integration is relatively new and has emerged to provide an alternate solution for high performance computation. This paper introduces a new routing algorithm which aims to improve performance characteristics of conventional existing algorithms. Volumetric Degenerative Routing, as proposed in this paper, reduces maximum delay by as much as 40%.