Challenges of CMOS scaling at below 0.1 μm

Author

Shahidi, Ghavam G.

Author_Institution

Adv. Silicon Technol. Center, IBM Corp., Hopewell Junction, NY, USA

fYear

2000

fDate

2000

Firstpage

5

Lastpage

8

Abstract

Over the last two decades, CMOS scaling has been the main driver of the electronics industry. During the last few years, the pace of scaling has been accelerating, and we are approaching some fundamental limits. In this paper, some of the key challenges of CMOS scaling, as we move into the 0.1 μm generation and beyond, are reviewed. They include challenges faced in short channel effects, gate oxide scaling, I _off and low voltage operation, metallization, and reliability. A few of the potential solutions to some of these problems are discussed. They include introduction of SOI and novel structures, high-k gate dielectrics, strained Si layers on SiGe, and low-T operation

Keywords

CMOS integrated circuits; cryogenic electronics; dielectric thin films; integrated circuit design; integrated circuit interconnections; integrated circuit measurement; integrated circuit metallisation; integrated circuit reliability; low-power electronics; permittivity; silicon-on-insulator; 0.1 micron; CMOS scaling; SOI structures; Si-SiGe; Si-SiO₂; SiGe; SiGe substrates; electronics industry; gate oxide scaling; high-k gate dielectrics; low voltage operation; low-temperature operation; metallization; off-state current; reliability; short channel effects; strained Si layers; Acceleration; CMOS technology; Circuits; Dielectrics; MOSFETs; Manufacturing; Moore´s Law; Switches; Technological innovation; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronics, 2000. ICM 2000. Proceedings of the 12th International Conference on

Conference_Location

Tehran

Print_ISBN

964-360-057-2

Type

conf

DOI

10.1109/ICM.2000.916402

Filename

916402