Title :
Design of A 10Gb/s in-line scalable Network Security Processor array
Author :
Niu, Yun ; Wu, Liji ; Xu, Jun
Author_Institution :
Nat. Lab. for Inf. Sci. & Technol., Tsinghua Univ., Beijing, China
Abstract :
Design of a Gigabit In-Line scalable Network Security Processor on one chip is presented. With 8 parallel chips array and some control logic, the design may be used in 10 Gigabit Ethernet. Moreover, custom-specific off-chip crypto algorithms can replace the standard one on the chip through pr-reserved data interface, which improves the scalability of the design in crypto operation.
Keywords :
cryptography; local area networks; microprocessor chips; telecommunication security; Ethernet; bit rate 10 Gbit/s; custom-specific off-chip crypto algorithm; parallel chips array; pr-reserved data interface; scalable network security processor array; Algorithm design and analysis; Coprocessors; Data security; Ethernet networks; Hardware; Information security; Protocols; Public key cryptography; Scalability; Search engines; Crypto Algorithm; Hardware implementation; Network Security Processor; Network Security Protocol;
Conference_Titel :
Wireless and Optical Communications Conference (WOCC), 2010 19th Annual
Conference_Location :
Shanghai
Print_ISBN :
978-1-4244-7597-1
DOI :
10.1109/WOCC.2010.5510643
