Title :
vMOS-based compressor designs
Author :
Quintana, Jose M. ; Avedillo, María J. ; Rodríguez-Villegas, Esther ; Rueda, Adoración
Author_Institution :
Centro Nacional de Microelectron., Inst. de Microelectron. de Sevilla, Spain
Abstract :
Partial-product reduction circuits (compressors) are of capital importance in the design of high performance parallel multipliers. This paper proposes compressor designs based on threshold gates which have been implemented as vMOS circuits. A typical block, a (4,2) compressor, is fully developed. Data for a (6,2) compressor are also provided. Results show that such compressors have the best performance in delay and power-delay product when compared to conventional implementations
Keywords :
MOS logic circuits; combinational circuits; delays; digital arithmetic; integrated circuit design; logic design; multiplying circuits; parallel processing; compressor block; compressor design; delay performance; parallel multiplier design; parallel multipliers; partial-product reduction circuits; power-delay product; threshold gates; vMOS circuits; vMOS-based compressor design; Adders; Combinational circuits; Delay; Energy consumption; Logic circuits; Logic gates; Microelectronics; Notice of Violation; Tree data structures; Wiring;
Conference_Titel :
Microelectronics, 2000. ICM 2000. Proceedings of the 12th International Conference on
Conference_Location :
Tehran
Print_ISBN :
964-360-057-2
DOI :
10.1109/ICM.2000.916409
