Title :
Design and implementation of high-speed JPEG image encoding system based on FPGA
Author :
Liu Rui ; Liu Peilin ; Zhao Hongxu
Author_Institution :
Dept. of Electron. Eng., Shanghai Jiao Tong Univ., Shanghai, China
Abstract :
This paper presents a design scheme of high-speed JPEG image encoding system based on FPGA. The encoder of this system can achieve the parallel processing of the input image sequences and work in pipeline mode. According to simulation test and FPGA verification, the whole system, which meets the JPEG standard for the requirements of image compression quality and compression ratio, can support the processing speed of 400fps for 1024x768 gray images, when the encoder core number is 4 and the working frequency is 100MHz. The high performance of the system can fully satisfy the demands of high speed and real time encoding applications.
Keywords :
data compression; field programmable gate arrays; image coding; image colour analysis; image sequences; parallel processing; pipeline processing; FPGA verification; JPEG standard; gray images; high-speed JPEG image encoding system; image compression quality; image compression ratio; image processing speed; image sequences; parallel processing; Discrete cosine transforms; Field programmable gate arrays; IP networks; Image coding; Real time systems; Registers; Transform coding; FPGA; JPEG; high-speed; image encoding system; real time;
Conference_Titel :
Multimedia Technology (ICMT), 2011 International Conference on
Conference_Location :
Hangzhou
Print_ISBN :
978-1-61284-771-9
DOI :
10.1109/ICMT.2011.6002418
