A full differential low voltage low power high speed current comparator

Author

Lahiji, G. Roientan ; Rezvan, F.

Author_Institution

Dept. of Electr. Eng., Iran Univ. of Sci. & Technol., Tehran, Iran

fYear

2000

fDate

2000

Firstpage

103

Lastpage

106

Abstract

A full differential low-voltage, low-power, and high-speed CMOS current comparator has been designed. The circuit is implemented using 0.5 μm CMOS technology and simulated using HSPICE. The comparison is performed in just one clock cycle with a sampling rate of 600 MHz, and can sense currents down to 0.1 μA (without considering the offset). The amount of offset obtained using Monte Carlo simulation is absolutely less than 0.4 μA for 95% of the cases. Power dissipation is less than 1 mW

Keywords

CMOS integrated circuits; Monte Carlo methods; SPICE; circuit simulation; current comparators; integrated circuit design; integrated circuit modelling; low-power electronics; 0.1 muA; 0.4 muA; 0.5 micron; 1 mW; 600 MHz; CMOS current comparator design; CMOS technology; HSPICE simulation; Monte Carlo simulation; clock cycle; current sensing; differential low voltage low power high speed current comparator; full differential low voltage low power high speed current comparator; high-speed CMOS current comparator; offset; power dissipation; sampling rate; CMOS technology; Clocks; Energy consumption; Latches; Low voltage; Power dissipation; Signal resolution; Switches; Switching circuits; Turning;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronics, 2000. ICM 2000. Proceedings of the 12th International Conference on

Conference_Location

Tehran

Print_ISBN

964-360-057-2

Type

conf

DOI

10.1109/ICM.2000.916424

Filename

916424