Zero-overhead BIST for internal-SRAM testing

We have developed an algorithm by which to enable conventional microprocessors to test their on-chip SRAM using their existing hardware and software resources. This test method utilizes a mixture of existing memory testing techniques, which cover all important memory faults. Memory fault diagnostic capabilities are also provided. This is achieved by writing a routine called BIST program which only uses the existing ROM and creates no additional hardware overhead. BIST program implements the “length 9N” test algorithm. The proposed test algorithm covers 100% of faults under the fault model plus a data retention test. Diagnostic capability is also provided by BIST program. This method can be implemented for internal memory testing of all microprocessors, microcontrollers and DSPs. This test algorithm is tested experimentally on the 32K SRAM cell of a Texas Instruments TMS320C548 DSP