The effect of gate orientation on fault detection

Author

Attarha, Amir ; Nourani, Mehrdad

Author_Institution

Dept. of EE, Texas Univ., Richardson, TX, USA

fYear

2000

fDate

2000

Firstpage

113

Lastpage

116

Abstract

Real defects (e.g. stuck-at or bridging faults) in VLSI circuits cause intermediate voltages and can not be modeled as ideal shorts. When a resistive (nonzero) fault model is used in fault detection, the gate orientation plays an important role. In this work, we discuss how a logically symmetrical gate may show electronically nonsymmetrical behavior and how such a property influences fault detection and test pattern generation of digital VLSI circuits

Keywords

CMOS digital integrated circuits; VLSI; automatic test pattern generation; fault diagnosis; integrated circuit modelling; integrated circuit testing; CMOS digital IC; VLSI circuits; bridging faults; defects; digital VLSI circuits; electronically nonsymmetrical behavior; fault detection; fault models; gate orientation; intermediate voltages; logically symmetrical gate; resistive nonzero fault model; stuck-at faults; test pattern generation; Bridge circuits; Circuit faults; Circuit simulation; Electrical fault detection; Fabrication; Fault detection; SPICE; Semiconductor device modeling; Very large scale integration; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronics, 2000. ICM 2000. Proceedings of the 12th International Conference on

Conference_Location

Tehran

Print_ISBN

964-360-057-2

Type

conf

DOI

10.1109/ICM.2000.916426

Filename

916426