Behavioral test generation for VHDL processes

Author

Gharehbaghi, Amir Masoud ; Navabi, Zainalabedin

Author_Institution

Dept. of Electr. & Comput. Eng., Tehran Univ., Iran

fYear

2000

fDate

2000

Firstpage

123

Lastpage

126

Abstract

In this paper, two test generation algorithms for VHDL processes are presented. The first algorithm works on combinational processes, whereas the second works on sequential processes. The goal of both algorithms is testing all portions of the design by traversing all the possible paths. The VHDL subset we have considered in these algorithms covers almost 90% of ordinary designs. Our approach in this paper employs software testing metrics as well as state and transition coverage for FSMs

Keywords

fault diagnosis; finite state machines; hardware description languages; high level synthesis; logic CAD; logic testing; software metrics; software reliability; FSMs; VHDL processes; VHDL subset; behavioral test generation; combinational processes; design testing; sequential processes; software testing metrics; state coverage; test generation algorithms; transition coverage; Algorithm design and analysis; Application software; Costs; Formal verification; Hardware design languages; Logic testing; Process design; Sequential analysis; Software metrics; Software testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronics, 2000. ICM 2000. Proceedings of the 12th International Conference on

Conference_Location

Tehran

Print_ISBN

964-360-057-2

Type

conf

DOI

10.1109/ICM.2000.916428

Filename

916428