Title :
Assessment of fully-depleted planar CMOS for low power complex circuit operation
Author :
Ren, Z. ; Mehta, S. ; Cai, J. ; Wu, S. ; Zhu, Y. ; Kanarsky, T. ; Kanakasabapathy, S. ; Edge, L.F. ; Zhang, R. ; Lindo, P. ; Koshy, J. ; Tabakman, K. ; Kulkarni, P. ; Sardesai, V. ; Cheng, K. ; Khakifirooz, A. ; Doris, B. ; Bu, H. ; Park, D.-G.
Author_Institution :
IBM SRDC, Hopewell Junction, NY, USA
Abstract :
In this paper, we present results and discuss issues related to implementation of large scale circuits in extremely thin (ET) SOI CMOS for low power applications. We have demonstrated that we can fabricate low power (LP) CMOS with centered Vts and good Vt uniformity across wafer and wafer to wafer. Using this CMOS, we have fabricated low leakage and high performance ring oscillators (with delay ~20% faster than the standard 28 nm LP bulk). We have also obtained perfect 2.25M SRAM arrays, functioning down to Vdd of 0.5V, and we have shown that a 10-level BEOL process has minimal impact on device stability.
Keywords :
CMOS memory circuits; SRAM chips; elemental semiconductors; low-power electronics; oscillators; silicon; silicon-on-insulator; 10-level BEOL process; LP CMOS; SRAM array; Si; extremely thin ET SOI CMOS; fully-depleted planar CMOS; large scale circuit; low power CMOS; low power application; low power complex circuit operation; ring oscillator; size 28 nm; storage capacity 2.25 Mbit; voltage 0.5 V; CMOS integrated circuits; Logic gates; Metals; Performance evaluation; Random access memory; Ring oscillators; Substrates;
Conference_Titel :
Electron Devices Meeting (IEDM), 2011 IEEE International
Conference_Location :
Washington, DC
Print_ISBN :
978-1-4577-0506-9
Electronic_ISBN :
0163-1918
DOI :
10.1109/IEDM.2011.6131560
