Title :
A correlation study of MOL electrical test method with its physical analysis
Author :
Cahyadi, Tommy ; Chen, Fan ; Jiang, Hongbo ; Mittl, S. ; Chua, E.C.
Author_Institution :
GLOBALFOUNDRIES U.S. Inc., Malta, NY, USA
Abstract :
A correlation study of middle-of-line (MOL) electrical test method with its inline polysilicon gate (PC) and the diffusion contacts (CA) photolithography overlay data is presented in this paper for wafers fabricated by gate first CMOS process at 32nm. The physical analysis by scanning electron microscopy (SEM) further confirmed the accuracy of the electrical test method in explaining the physical values of global shift and local shift. Therefore, this electrical PC-to-CA testing methodology can be adopted cost effectively for an accurate MOL reliability assessment and process diagnostics in a timely and comprehensive manner.
Keywords :
CMOS integrated circuits; elemental semiconductors; integrated circuit reliability; integrated circuit testing; photolithography; scanning electron microscopy; silicon; CA photolithography overlay data; MOL electrical test method; MOL reliability assessment; SEM; Si; diffusion contact photolithography overlay data; electrical PC-to-CA testing methodology; electrical test method; gate first CMOS process; global shift; inline PC; inline polysilicon gate; local shift; middle-of-line electrical test method; physical analysis; process diagnostics; scanning electron microscopy; size 32 nm; wafer fabrication; Correlation; Logic gates; Optical imaging; Optical variables measurement; Presses; Reliability; Scanning electron microscopy; MOL; Middle-of-Line; PC-to-CA overlay; PC-to-CA reliability; PC-to-CA space; VRDB; fatal-area ratio; global variation; local variation;
Conference_Titel :
Physical and Failure Analysis of Integrated Circuits (IPFA), 2013 20th IEEE International Symposium on the
Conference_Location :
Suzhou
Print_ISBN :
978-1-4799-1241-4
DOI :
10.1109/IPFA.2013.6599156
