A Low-Power Safety Mode for Variation Tolerant Systems-on-Chip

Process, voltage, and temperature (PVT) variations are difficult to manage in multi-core SoCs, as each core may have different voltage and reliability requirements. Indeed, common implementations of variation-tolerant techniques (e.g. dynamic voltage and frequency scaling) are ineffective in multi-core SoCs because of the large overheads they incur. In this work, we propose a simple low-power safety-mode system that adjusts each corepsilas frequency independently to compensate for PVT variation at runtime. This module combines an on-chip sensor with a safety-mode lookup table to guarantee SoC functionality. The module is simulated in a four-core SoC framework, and allows the system to operate at a frequency corresponding to the average system temperature instead of the worst-case temperature. In the case presented, a room temperature system is capable of operating at an average frequency that is 2X that of the worst-case temperature requirements. The safety mode module consumes an average power of 0.56 muW and has a 3% area overhead.