• DocumentCode
    3037913
  • Title

    Obtaining Microprocessor Vulnerability Factor Using Formal Methods

  • Author

    Shazli, Syed Z. ; Tahoori, Mehdi B.

  • Author_Institution
    Northeastern Univ., Boston, MA
  • fYear
    2008
  • fDate
    1-3 Oct. 2008
  • Firstpage
    63
  • Lastpage
    71
  • Abstract
    Aggressive technology down-scaling increases the vulnerability of microprocessors to runtime errors, in particular radiation-induced soft errors. In this paper, we present a technique based on Boolean satisfiability (SAT) to obtain reliability parameters of microprocessors in the presence of soft errors. We use a metric called microprocessor vulnerability factor (MVF) which captures the soft error rate of a particular implementation of the microprocessor, separating it from vulnerability factors due to the micro-codes and programs running on the microprocessor. We transform the MVF computation problem into equivalent Boolean satisfiability problem and use state-of-the-art SAT-solvers to obtain MVF. We present results for some widely used RISC processor cores and provide detailed analysis for various instructions and execution paths/resources.
  • Keywords
    Boolean functions; circuit reliability; microprocessor chips; Boolean satisfiability; down-scaling technology; formal method; microprocessor vulnerability factor; radiation-induced soft error; reliability parameter; state-of-the-art SAT-solver; Circuit faults; Error analysis; Fault tolerant systems; Hardware; Logic devices; Logic gates; Microprocessors; Reduced instruction set computing; Runtime; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Defect and Fault Tolerance of VLSI Systems, 2008. DFTVS '08. IEEE International Symposium on
  • Conference_Location
    Boston, MA
  • ISSN
    1550-5774
  • Print_ISBN
    978-0-7695-3365-0
  • Type

    conf

  • DOI
    10.1109/DFT.2008.52
  • Filename
    4641158