Cache design for high performance computers with BiCMOS VLSIs

Author

Morioka, M. ; Kurita, K. ; Kobayashi, H. ; Sawamoto, H.

Author_Institution

Hitachi Ltd., Ibaraki, Japan

fYear

1990

fDate

17-19 Sep 1990

Firstpage

413

Lastpage

416

Abstract

Cache memory architectures and BiCMOS circuit technologies for high-speed access time that take advantage of the high integration level are discussed. Proposed is a VLSI-oriented cache memory architecture, which reduces the penalty of chip-crossings, and a functional BiCMOS RAM with gate-array suited to the associative function of the cache memory. BiCMOS cache chip sets are developed for high-performance computers with 0.8-μm BiCMOS technology. The BiCMOS cache memory can improve the cost-performance of cache systems due to high-speed access time and high density

Keywords

BIMOS integrated circuits; VLSI; buffer storage; integrated memory circuits; memory architecture; random-access storage; 0.8 micron; BiCMOS VLSIs; RAM; access time; associative function; cache memory architecture; cost-performance; gate-array; high density; high performance computers; BiCMOS integrated circuits; CMOS technology; Cache memory; Central Processing Unit; High performance computing; Memory architecture; Microprocessors; Random access memory; Technical Activities Guide -TAG; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design: VLSI in Computers and Processors, 1990. ICCD '90. Proceedings, 1990 IEEE International Conference on

Conference_Location

Cambridge, MA

Print_ISBN

0-8186-2079-X

Type

conf

DOI

10.1109/ICCD.1990.130265

Filename

130265