A High-Speed Variation-Tolerant Interconnect Technique for Sub-Threshold Circuits Using Capacitive Boosting

Author

Kil, J. ; Gu, Jie ; Kim, Chris H.

Author_Institution

Intel Corp., Folsom, CA

fYear

2006

fDate

4-6 Oct. 2006

Firstpage

67

Lastpage

72

Abstract

This paper describes an interconnect technique for sub-threshold circuits to improve global wire delay and reduce the delay variation due to PVT fluctuations. By internally boosting the gate voltage of the driver transistors, operating region is shifted from sub-threshold region to super-threshold region enhancing performance and improving tolerance to PVT variations. A clock distribution network using the proposed drivers shows an 89% reduction in 3sigma clock skew value. A 0.4V test chip has been fabricated in a 0.18mum 6-metal CMOS process to demonstrate the effectiveness of the proposed scheme. Measurement results show 2.6times faster switching speed and 2.4times less delay sensitivity under temperature variations

Keywords

CMOS integrated circuits; delays; driver circuits; integrated circuit design; integrated circuit interconnections; 0.18 micron; 0.4 V; 6-metal CMOS process; PVT fluctuations; capacitive boosting; clock distribution network; delay variation; driver transistors; gate voltage; global wire delay; sub-threshold circuits; variation-tolerant interconnect technique; Boosting; CMOS process; Clocks; Delay; Driver circuits; Fluctuations; Integrated circuit interconnections; Testing; Voltage; Wire; Design; Global interconnect; Measurement; Performance; capacitive boosting; clock skew; sub-threshold circuit; variation tolerance;

fLanguage

English

Publisher

ieee

Conference_Titel

Low Power Electronics and Design, 2006. ISLPED'06. Proceedings of the 2006 International Symposium on

Conference_Location

Tegernsee

Print_ISBN

1-59593-462-6

Type

conf

DOI

10.1109/LPE.2006.4271809

Filename

4271809