Title :
Time-Borrowing Multi-Cycle On-Chip Interconnects for Delay Variation Tolerance
Author :
Bowman, Keith ; Tschanz, James ; Khellah, Muhammad ; Ghoneima, Maged ; Ismail, Yousr ; De, Vivek
Author_Institution :
Intel Corp., Hillsboro, OR
Abstract :
Insertion of time-borrowing (TB) flip-flops in multi-cycle repeater-based on-chip interconnects enables significant improvements in mean performance and energy by averaging systematic and random within-die (WID) delay variations across multiple interconnect segments. A statistically-based analytical model is derived to design a TB N-cycle interconnects with optimal delay variation tolerance. The model elucidates the dependency of the transparency window required to achieve data delay averaging on the delay variation mismatch between interconnect segments. Statistical circuit simulations and analyses in a 65nm process technology demonstrate that TB multi-cycle interconnects enable a 4-6% mean maximum clock frequency (FMAX) improvement and a corresponding 10% average energy savings over optimally designed multi-cycle interconnects with conventional master-slave flip-flops. The maximum mean FMAX benefit ranges from 4.0-7.5%, corresponding to approximately a bin-split shift in the FMAX distribution. For 1.41X larger WID delay variations, the maximum mean FMAX gain rises to 5-10%
Keywords :
circuit simulation; flip-flops; integrated circuit interconnections; integrated circuit modelling; logic design; statistical analysis; 65 nm; data delay averaging; delay variation mismatch; delay variation tolerance; master-slave flip-flops; multicycle repeater-based on-chip interconnects; multiple interconnect segments; statistical circuit simulations; statistically-based analytical model; time-borrowing flip-flops; time-borrowing multicycle on-chip interconnects; transparency window; within-die delay variations; Analytical models; Circuit analysis; Circuit simulation; Clocks; Delay; Flip-flops; Frequency; Integrated circuit interconnections; Repeaters; System-on-a-chip; Algorithm; Parameter fluctuations; design; interconnect; intra-die variations; multi-cycle interconnect; parameter variations; performance; reliability; time borrowing; variation tolerant; within-die variations;
Conference_Titel :
Low Power Electronics and Design, 2006. ISLPED'06. Proceedings of the 2006 International Symposium on
Conference_Location :
Tegernsee
Print_ISBN :
1-59593-462-6
DOI :
10.1109/LPE.2006.4271811