Title :
A new SSS-OSELO technology for 0.15-/spl mu/m low-defect isolation
Author :
Sudoh, Y. ; Kaga, T. ; Yugami, J. ; Kure, T.
Author_Institution :
Central Res. Lab., Hitachi Ltd., Tokyo, Japan
Abstract :
A new isolation with single-Si/sub 3/N/sub 4/-spacer (SSS) OSELO technology is proposed. The features of the SSS OSELO process are low bird´s beak penetration and low defect isolation, which are achieved by using low defect-density etching for the Si/sub 3/N/sub 4/ spacer formation, and lower growth-rate and/or a high-temperature oxidation ambient. The SSS OSELO technology allows the 0.15-/spl mu/m low-defect isolation and the fabrication of 1-gigabit DRAM cells.
Keywords :
DRAM chips; integrated circuit technology; isolation technology; oxidation; 0.15 micron; 1 Gbit; DRAM cells; SSS-OSELO technology; Si/sub 3/N/sub 4/; bird´s beak; etching; fabrication; growth; high-temperature oxidation; low-defect isolation; single-Si/sub 3/N/sub 4/-spacer; Dry etching; Fabrication; Hafnium; Isolation technology; Oxidation; Semiconductor films; Space technology; Stress; Substrates; Temperature;
Conference_Titel :
VLSI Technology, 1995. Digest of Technical Papers. 1995 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
0-7803-2602-4
DOI :
10.1109/VLSIT.1995.520885
