A Digital BIST for Phase-Locked Loops

Author

Sliech, Kevin ; Margala, Martin

Author_Institution

Electr. & Comput. Eng. Dept., Univ. of Massachusetts Lowell, Lowell, MA

fYear

2008

fDate

1-3 Oct. 2008

Firstpage

134

Lastpage

142

Abstract

This paper presents a conceptual implementation of a jitter measurement circuit with several BIST (built-in self test) features for embedded phase-locked loops. We demonstrate a fully functional jitter measurement circuit capable of detecting cycle-to-cycle jitter. Proposed BIST logic provides additional information such as MAX jitter value, programmable threshold detection and most recent jitter result with low processing overhead.

Keywords

built-in self test; jitter; phase locked loops; MAX jitter value; built-in self test; cycle-to-cycle jitter; digital BIST; functional jitter measurement circuit; phase-locked loops; programmable threshold detection; Built-in self-test; CMOS logic circuits; Capacitors; Circuit testing; Frequency measurement; Jitter; Logic circuits; Phase detection; Phase locked loops; Phase measurement; BIST; Digital; Jitter; PLL;

fLanguage

English

Publisher

ieee

Conference_Titel

Defect and Fault Tolerance of VLSI Systems, 2008. DFTVS '08. IEEE International Symposium on

Conference_Location

Boston, MA

ISSN

1550-5774

Print_ISBN

978-0-7695-3365-0

Type

conf

DOI

10.1109/DFT.2008.62

Filename

4641166

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3038092