Title :
Analyzing the Impact of Fault-tolerant BIST for VLSI Design
Author :
Daasch, W. Robert ; Jain, Saurabh X. ; Armbrust, David X.
Author_Institution :
Dept. of Electr. & Comput. Eng., Portland State Univ., Portland, OR
Abstract :
This paper examines fault-tolerant DfT (Design for Test) circuits as an effective approach for improved reliability and lower defective parts per million (DPPM). The paper provides a comprehensive examination of one alternative, quadded gate, inter-leaved node logic design. Quadded DfT circuitry is compared to circuitry with no fault tolerance in terms of area, power and performance. Ever shrinking device sizes are challenging the reliability limits and testing capabilities of a modern day integrated circuit (IC). Parametric variations, higher gate counts and lower pin counts render fault avoidance techniques ineffective and make fault detection an engineering challenge. Higher defect rates and Ultra Large Scale Integration (ULSI) will require bigger and complex DfT circuitry. This will result in more chips being rejected due to DfT failures. Fault-tolerant DfT directly translates to shorter time-to-market, increased reliability and improved yield learning.
Keywords :
VLSI; built-in self test; design for testability; integrated circuit reliability; logic design; logic testing; VLSI design; built-in self test; design for test; fault-tolerant BIST; interleaved node logic design; Built-in self-test; Circuit faults; Circuit testing; Design for testability; Fault tolerance; Integrated circuit reliability; Integrated circuit testing; Logic design; Ultra large scale integration; Very large scale integration; Built-in Self Test (BIST); Defect and Fault Tolerance; Design for Test (DFT); Error Correction; Quadded Logic; Yield Learning;
Conference_Titel :
Defect and Fault Tolerance of VLSI Systems, 2008. DFTVS '08. IEEE International Symposium on
Conference_Location :
Boston, MA
Print_ISBN :
978-0-7695-3365-0
DOI :
10.1109/DFT.2008.55
