A fast cycle-based approach for synthesizable RT level VHDL simulation

In this paper, a cycle-based RT level simulation engine is being discussed. Issues treated include component extraction, component ordering and feedback detection from behavioral VHDL descriptions. Proposing new methods in these topics, we try to give solutions for the problems that VHDL register transfer level simulators have to deal with. We also introduce a levelization method that due to its compatibility with the nature of RTL VHDL increases the simulation speed