A BIST Technique for Crosstalk Noise Detection in FPGAs

As integrated circuits are migrated to more advanced technologies, it has become clear that crosstalk noise is an important phenomenon that must be taken into account. Also, crosstalk noise has emerged as a serious problem in recent years, because more and more devices and wires have been packed on electronic chips. Despite being more immune to crosstalk noise than their ASIC (application specific integrated circuit) counterparts, the dense interconnected structures of FPGAs (field programmable gate arrays) invite more vulnerabilities to crosstalk noise. Due to the lack of electrical detail concerning FPGA devices it is quite difficult to test the faults caused by crosstalk noise. This paper proposes a new approach for detecting effects such as glitches and delays in transition due to crosstalk noise in FPGAs. This approach is similar to the BIST (built-in self test) technique in that it incorporates the test pattern generator to generate the test vectors and the analyzer to analyze the crosstalk faults without any extra overhead for testing.