Energy-efficient Motion Estimation using Error-Tolerance

Author

Varatkar, Girish V. ; Shanbhag, Naresh R.

Author_Institution

Illinois Univ., Urbana, IL

fYear

2006

fDate

4-6 Oct. 2006

Firstpage

113

Lastpage

118

Abstract

Presented is an energy-efficient motion estimation architecture using error-tolerance. The technique employs overscaling of the supply voltage (voltage overscaling (VOS)) to reduce power at the expense of timing errors, which are then corrected using algorithmic noise-tolerance (ANT) techniques. Referred to as input subsampled replica ANT (ISR-ANT), the proposed technique incorporates an input subsampled replica of the main sum of absolute difference (MSAD) block for obtaining the motion vectors in the presence of errors induced by VOS. Simulations show that the proposed technique can save up to 60% power over an optimal error-free present day system in a 130nm CMOS technology. Power savings increase to 79% in a 45nm predictive process technology

Keywords

CMOS digital integrated circuits; logic design; low-power electronics; microprocessor chips; motion estimation; 130 nm; 45 nm; CMOS technology; algorithmic noise-tolerance; energy-efficient motion estimation architecture; error-tolerance; input subsampled replica ANT; motion vectors; supply voltage; timing errors; voltage overscaling; Algorithm design and analysis; CMOS technology; Digital video broadcasting; Energy consumption; Energy efficiency; Error correction; Motion estimation; Power system reliability; Timing; Voltage; Algorithms; Design; Low-power; Reliability; noise-tolerance;

fLanguage

English

Publisher

ieee

Conference_Titel

Low Power Electronics and Design, 2006. ISLPED'06. Proceedings of the 2006 International Symposium on

Conference_Location

Tegernsee

Print_ISBN

1-59593-462-6

Type

conf

DOI

10.1109/LPE.2006.4271817

Filename

4271817