Variability-Aware Device Optimization under ION and Leakage Current Constraints

Author

Jaffari, Javid ; Anis, Mohab

Author_Institution

Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont.

fYear

2006

fDate

4-6 Oct. 2006

Firstpage

119

Lastpage

122

Abstract

In this paper, a novel device optimization methodology is presented that is constrained by the total leakage and the ON current of the device. The devised technique locates a maximum yield rectangular cube in a three-dimensional feasible space composed by oxide thickness, halo peak doping, and halo characteristic length parameters. The center of this cube is considered as the maximum yield design point with the highest immunity against variations. Monte Carlo simulations show that the optimized bulk-MOS device for 45 nm gate length satisfies the on current and leakage constraints under a variability of up to 30% in the three parameters

Keywords

Monte Carlo methods; integrated circuit design; integrated circuit modelling; leakage currents; 45 nm; Monte Carlo simulations; bulk-MOS device; halo characteristic length parameters; halo peak doping; leakage current constraints; maximum yield design point; maximum yield rectangular cube; oxide thickness; variability-aware device optimization; Algorithm design and analysis; Analytical models; CMOS technology; Constraint optimization; Design methodology; Doping profiles; Leakage current; Permission; Process design; Silicon; Algorithms; Design; Device Design; Leakage Current; Optimization; Performance; Process Variation; Reliability;

fLanguage

English

Publisher

ieee

Conference_Titel

Low Power Electronics and Design, 2006. ISLPED'06. Proceedings of the 2006 International Symposium on

Conference_Location

Tegernsee

Print_ISBN

1-59593-462-6

Type

conf

DOI

10.1109/LPE.2006.4271818

Filename

4271818