A 0.5-V FD-SOI Twin-Cell DRAM with Offset-Free Dynamic-VT Sense Amplifiers

Author

Takemura, Riichiro ; Itoh, Kiyoo ; Sekiguchi, Tomonori

Author_Institution

Central Res. Lab., Hitachi Ltd., Tokyo

fYear

2006

fDate

4-6 Oct. 2006

Firstpage

123

Lastpage

126

Abstract

Three DRAM technologies, which are a leakage- and soft-error-free planar-capacitor SOI cell, a data-line shielded twin (2-T) cell array, and an offset-free dynamic-V_T sense amplifier suitable for low-voltage mid-point sensing, are presented and evaluated. New noise-generation mechanisms are also shown. Using the experimental data of an ultrathin BOX double-gate fully-depleted SOI MOST, a 1.5-ns cycle-time 65-nm 2-kb subarray was found to be feasible for embedded applications, even at 0.5 V

Keywords

DRAM chips; MOSFET; amplifiers; capacitors; silicon-on-insulator; 0.5 V; 1.5 ns; 65 nm; DRAM technologies; double-gate fully-depleted SOI MOST; fully depleted silicon-on-insulator DRAM; leakage-free planar-capacitor SOI cell; low-voltage mid-point sensing; noise-generation mechanisms; offset-free dynamic-V_T sense amplifiers; soft-error-free planar-capacitor SOI cell; twin-cell DRAM; ultrathin buried oxide SOI MOST; Application specific integrated circuits; Computed tomography; Integrated circuit noise; Integrated circuit technology; Laboratories; Logic arrays; Random access memory; Read-write memory; Signal to noise ratio; Voltage control; Design; FD-SOI; Performance; dynamic-VT sense amplifier; low-voltage RAM; twin-cell DRAM;

fLanguage

English

Publisher

ieee

Conference_Titel

Low Power Electronics and Design, 2006. ISLPED'06. Proceedings of the 2006 International Symposium on

Conference_Location

Tegernsee

Print_ISBN

1-59593-462-6

Type

conf

DOI

10.1109/LPE.2006.4271819

Filename

4271819