An 8 b 650 MHz folding ADC

Where a flash analog-to-digital converter (ADC) needs 2/sup N/-1 comparators to convert an analog value into an N-bit binary code, an M-times folding ADC can perform this function needing slightly more than 2/sup N//M comparators. In the design reported, N=8 and the folding factor M=8. Reduction in the number of comparators is obtained by analog preprocessing of the ADC input signal. In the design considered, power consumption, chip area, and parasitic capacitance at the analog input of the ADC are reduced by using only four folding blocks and 8-times interpolation.<>