Title :
A New Mismatch-Dependent Low Power Technique with Shadow Match-Line Voltage-Detecting Scheme for CAMs
Author :
Zhang, Jianwei ; Ye, Yizheng ; Liu, Binda
Author_Institution :
Microelectron. Center, Harbin Inst. of Technol.
Abstract :
A new mismatch-dependent low-power technique is presented for content-addressable memories (CAMs). With a novel shadow match-line voltage-detecting scheme, the word circuits realize fast self-disable of the charging paths in case of mismatches. Since the majority of CAMs words are mismatched, a significant power is reduced with a high search speed. Simulation results show the proposed 256-word times 144-bit ternary CAM, using 0.13-mum 1.2-V CMOS process, achieves 0.51 fJ/bit/search for the word circuit with less than 900 ps search time. The achievement illustrates a 77% energy-delay-product (EDP) reduction as compared to the speed-optimized current-saving scheme
Keywords :
CMOS memory circuits; content-addressable storage; low-power electronics; 0.13 micron; 1.2 V; CMOS process; content-addressable memories; energy-delay-product reduction; fast self-disable; mismatch-dependent low-power technique; shadow match-line voltage-detecting scheme; ternary CAM; Application software; CADCAM; CMOS process; Cams; Circuit simulation; Computer aided manufacturing; Driver circuits; Microelectronics; Multilevel systems; Voltage; CAM; Design; Performance; high speed; low power; mismatch-dependent; voltage detecting;
Conference_Titel :
Low Power Electronics and Design, 2006. ISLPED'06. Proceedings of the 2006 International Symposium on
Conference_Location :
Tegernsee
Print_ISBN :
1-59593-462-6
DOI :
10.1109/LPE.2006.4271822
