Carbon nanotube electronics - Materials, devices, circuits, design, modeling, and performance projection

This paper summarizes a multi-disciplinary effort to realize the high expectations of the use of carbon nanotube (CNT) as a material for highly energy-efficient future digital systems. Today CNTs are grown on full wafers, highly aligned in one direction, and subsequently transferred to a target substrate multiple times for increased CNT density. Device level performance of carbon nanotube transistor (CNFET) rivals the best silicon transistor. Inherent CNT imperfections such as mis-positioned and metallic CNTs have been overcome through a combination of processing and imperfection-immune design techniques. As a result, CNFET-based digital arithmetic and storage circuit are fabricated using conventional optical lithography steppers and fabrication tools, some of them at full wafer scale. CNT interconnects with sub-ns delays have been measured using ring oscillators. Physics-based analytical and compact models have been developed to enable circuit design, circuit-level analysis of CNT-specific variations, and performance projection at the device, circuit, and system level. It is projected that CNFET circuits can enable 5x speed-up at the same power consumption over Si CMOS(PDSOI) at the 11 nm technology node for a four-core processor with 1.5M logic gates and 5MB SRAM per core. CNFET is the only FET that is projected to outperform the 11 nm node ITRS target.