Title :
A 12 b 5 MS/s two-step CMOS A/D converter
Author :
Razavi, B. ; Wooley, B.A.
Author_Institution :
Center for Integrated Sys., Stanford Univ., CA, USA
Abstract :
A 12 b 5 MHz fully differential two-step ADC (analog-to-digital converter) is described which is integrated in a 1- mu m CMOS technology, uses both analog and digital correction, and dissipates 200 mW. The ADC architecture and timing diagram are shown.<>
Keywords :
CMOS integrated circuits; analogue-digital conversion; error correction; 1 micron; 12 bit resolution; 200 mW; 5 MHz; ADC architecture; CMOS A/D converter; digital correction; fully differential two-step ADC; CMOS process; Capacitors; Contracts; EPROM; Merging; Power supplies; Recycling; Solid state circuits; Timing; Very large scale integration;
Conference_Titel :
Solid-State Circuits Conference, 1992. Digest of Technical Papers. 39th ISSCC, 1992 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-0573-6
DOI :
10.1109/ISSCC.1992.200398
