Quantifying LER to predict its impact on BEOL TDDB reliability at 20nm ½ pitch

Author

Demuynck, S. ; Roussel, Ph ; Stucchi, M. ; Versluijs, J. ; Gishia, G.G. ; De Roest, D. ; Tökei, Zs ; Beyer, G.P.

Author_Institution

IMEC, Leuven, Belgium

fYear

2010

fDate

6-9 June 2010

Firstpage

1

Lastpage

3

Abstract

We present results of a refined model that allows prediction of the influence of LER on the TDDB performance when scaling towards 20nm ½ pitch. The model is validated on 35nm ½ pitch state-of-the-art Cu/low-k interconnects, defined in a double patterning integration scheme, using wafer-level TDDB measurements and in-line post-CMP evaluation of both low-k space and parameters describing LER. The results predict a 9 orders of magnitude reduction in TDDB lifetime at 20nm ½ pitch in case uncor-related LER is not scaling, but no further degradation due to protrusions in the dielectric space.

Keywords

chemical mechanical polishing; copper; integrated circuit interconnections; integrated circuit reliability; low-k dielectric thin films; BEOL TDDB reliability; Cu; Cu low-k interconnects; LER; double patterning integration scheme; in-line post-CMP evaluation; line-edge roughness; wafer-level TDDB measurements; Degradation; Dielectric breakdown; Dielectric measurements; Electronic mail; Etching; Extraterrestrial measurements; Life testing; Predictive models; Semiconductor device modeling; Tin;

fLanguage

English

Publisher

ieee

Conference_Titel

Interconnect Technology Conference (IITC), 2010 International

Conference_Location

Burlingame, CA

Print_ISBN

978-1-4244-7676-3

Type

conf

DOI

10.1109/IITC.2010.5510698

Filename

5510698