Realization of L2 Cache Defect Tolerance Using Multi-bit ECC

This paper presents a design solution that enables the use of powerful multi-bit error-correcting code (ECC) to realize L2 cache defect tolerance at minimal latency and silicon area cost. This work is motivated by the observation that the continuous CMOS Technology scaling may result in an increasing level defect density and make conventional cache memory defect tolerance strategies inadequate. The basic idea is to complement conventional L2 cache core with two separate fully associative caches, one stores multi-bit ECC check bits for realizing area-efficient selective multi-bit ECC protection and another one stores the most recently decoded multi-bit ECC code word to minimize the impact of explicit multi-bit ECC decoding on L2 cache access latency. Its effectiveness has been demonstrated using SimpleScalar and Cacti tools. At the defect density of 0.5%, this design approach can maintain almost the same instruction per cycle (IPC) performance over a wide spectrum of benchmarks compared with ideal L2 cache without defects, while only incurring less than 2.5% of silicon area overhead.