A 17 b algorithmic ADC

An analog-to-digital converter (ADC) is presented which uses auto gain-ranging to achieve signal amplification without the associated amplification of input-referred errors. The part, fabricated in a BiCMOS process, has a 108-dB dynamic range limited by white noise and DC errors <20 mu V. The system consists of an input multiplexer, two sample and holds (SHAs), an error amplifier, precision resistor/switch network, a window comparator and a CMOS gate array. Systematic offsets in the SHAs, noise in the loop, and gain accuracies (determined by resistor ratios) are the critical design parameters. The design challenge is to optimize the noise within the system bandwidth and remove all nonlinear forms of error. Performance in the time domain when a decaying exponential voltage with an 80-ms time constant is applied at the input is shown.<>