Title :
0.5 mu m BiCMOS standard-cell macros including 0.5 W 3 ns register file and 0.6 W 5 ns 32 kB cache
Author :
Kara, H. ; Sakurai, T. ; Nagamatsu, T. ; Kobayashi, S. ; Seta, K. ; Momose, H. ; Niitsu, Y. ; Miyakawa, H. ; Kuroda, T. ; Matsuda, K. ; Watanabe, Y. ; Sano, F. ; Chiba, A.
Author_Institution :
Toshiba Corp., Kawasaki, Japan
Abstract :
BiCMOs standard-cell macros, including a 0.5-W, 3.0-ns register file, a 0.6-W, 5.0-ns 32-kB cache, a 0.2-W, 2.5-ns table look-aside buffer (TLB), and a 0.1-W, 3.0-ns adder, are presented based on a 0.5- mu m BiCMOs technology. These power consumption values are at 100 MHz operation. Low power and high speed are crucial for high-performance systems requiring a high level of integration. Several BiCMOS/CMOS circuits achieve high-speed operation with a 3.3-V supply. A direct-coupled ECL (emitter-coupled logic)+CMOS circuit is investigated for use as a BiCMOS standard cell.<>
Keywords :
BiCMOS integrated circuits; application specific integrated circuits; digital integrated circuits; 0.1 to 0.6 W; 0.5 micron; 100 MHz; 2.5 to 5 ns; 3.3 V; 32 kByte; ASIC; BiCMOS; CMOS circuit; adder; cache; direct-coupled ECL; emitter-coupled logic; high-speed operation; power consumption; register file; standard-cell macros; table look-aside buffer; Added delay; Adders; BiCMOS integrated circuits; Energy consumption; Latches; MOS devices; Propagation delay; Random access memory; Timing; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 1992. Digest of Technical Papers. 39th ISSCC, 1992 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-0573-6
DOI :
10.1109/ISSCC.1992.200403
