Computing in memory architectures for digital image processing

Author

Roth, Luke ; Coraor, Lee ; Landis, David ; Hulina, Paul ; Deno, Scott

Author_Institution

Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA

fYear

1999

fDate

1999

Firstpage

8

Lastpage

15

Abstract

Continuing improvements in semiconductor fabrication density are enabling new classes of system-on-a-chip architectures that combine extensive processing logic and high-density memory. Many of the capabilities of these new architectures can be custom tailored to the demands of real-time digital image processing. This paper evaluates several candidate designs, using the criteria of image processing performance, flexibility, manufacturability, and fabrication cost

Keywords

application specific integrated circuits; image processing equipment; memory architecture; real-time systems; fabrication cost; flexibility; high-density memory; image processing performance; manufacturability; memory architectures; processing logic; real-time digital image processing; semiconductor fabrication density; system-on-a-chip architectures; Computer architecture; Costs; Digital images; Fabrication; Image processing; Logic; Manufacturing processes; Memory architecture; Pulp manufacturing; System-on-a-chip;

fLanguage

English

Publisher

ieee

Conference_Titel

Memory Technology, Design and Testing, 1999. Records of the 1999 IEEE International Workshop on

Conference_Location

San Jose, CA

ISSN

1087-4852

Print_ISBN

0-7695-0259-8

Type

conf

DOI

10.1109/MTDT.1999.782678

Filename

782678