Title :
An Efficient Chip-level Time Slack Allocation Algorithm for Dual-Vdd FPGA Power Reduction
Author :
Lin, Yan ; Hu, Yu ; He, Lei ; Raghunat, Vijay
Author_Institution :
Dept. of Electr. Eng., UCLA, Los Angeles, CA
Abstract :
To reduce FPGA power, a linear programming (LP) based time slack allocation algorithm, EdTLC-LP, has been proposed recently for Vdd-programmable interconnects without using Vdd-level converters for mixed wire lengths. However, it takes a long time to solve the LP problem for time slack allocation. In this paper, we develop EdTLC-NW, a slack allocation algorithm based on min-cost network flow to reduce runtime. Compared to single Vdd FPGA with power-gating, EdTLC-LP and EdTLC-NW reduce interconnect power by 52.71% and 52.52%, respectively. EdTLC-NW achieves as good results as EdTLC-LP but runs 8times faster on average. Furthermore, the speedup increases for larger circuits and EdTLC-NW is 20times faster for the largest circuit
Keywords :
field programmable gate arrays; integrated circuit design; integrated circuit interconnections; logic design; low-power electronics; EdTLC-NW slack allocation algorithm; FPGA power reduction; Vdd-level converters; Vdd-programmable interconnects; chip-level time slack allocation algorithm; field programmable gate array; interconnect power reduction; linear programming; time slack allocation; Algorithm design and analysis; Field programmable gate arrays; Integrated circuit interconnections; Linear programming; Logic; Routing; Runtime; Switches; Switching converters; Wire; Algorithms; Design; FPGA; Low power; time slack;
Conference_Titel :
Low Power Electronics and Design, 2006. ISLPED'06. Proceedings of the 2006 International Symposium on
Conference_Location :
Tegernsee
Print_ISBN :
1-59593-462-6
DOI :
10.1109/LPE.2006.4271830
