Title :
A low-power multi-modulus divider in 0.6 μm digital CMOS technology
Author :
Zarei, Hossein ; Shoaei, Omid ; Fakraie, S.M. ; Zakeri, M.M.
Author_Institution :
Electr. & Comput. Dept., Tehran Univ., Iran
Abstract :
A 1.4 GHz programmable divider, whose modulus can be varied from 16 to 31, is presented with improved timing of the multi-modulus divider structure and high-speed low-voltage embedded logic D-flip flop. Programmability is achieved by gating the feedback signal of the first latch of the divide-by-2 blocks. For high-speed operation, the first control stage is implemented with a simple pseudo-NMOS logic gate. The programmable divider has been simulated in a 0.6 μm digital CMOS technology with 13 mW power consumption at 2.7 V power supply and 1.4 GHz maximum frequency
Keywords :
CMOS logic circuits; circuit feedback; circuit simulation; dividing circuits; flip-flops; integrated circuit design; logic CAD; logic gates; logic simulation; low-power electronics; programmable logic devices; timing; 0.6 micron; 1.4 GHz; control stage implementation; digital CMOS technology; divide-by-two blocks; feedback signal gating; high-speed low-voltage embedded logic D-flip flop; high-speed operation; low-power multi-modulus divider; maximum frequency; modulus variability; multi-modulus divider structure; power consumption; power supply; programmability; programmable divider; programmable divider simulation; pseudo-NMOS logic gate; timing; CMOS logic circuits; CMOS technology; Communication industry; Delay; Electronic mail; Frequency conversion; Frequency synthesizers; Logic circuits; Power dissipation; Timing;
Conference_Titel :
Microelectronics, 2000. ICM 2000. Proceedings of the 12th International Conference on
Conference_Location :
Tehran
Print_ISBN :
964-360-057-2
DOI :
10.1109/ICM.2000.916477
