A 9.5 Gb/s Si bipolar ECL array

Author

Tamamura, M. ; Shiotsu, S. ; Hojo, M. ; Nomura, K. ; Ichikawa, H. ; Akai, T.

Author_Institution

Fujitsu Ltd., Kawasaki, Japan

fYear

1992

fDate

19-21 Feb. 1992

Firstpage

54

Lastpage

55

Abstract

The authors describe a 9.5-Gb/s Si bipolar ECL (emitter coupled logic) gate which has performance approximately equal to that of custom ICs because of optimized ECL circuit design, 0.3- mu m Si bipolar process, and 10-GHz package technology. 9.5-GHz operation is obtained with 1-mA switching current and 0.3*5.5 mu m/sup 2/ emitter area because emitter current density (J/sub e/) for shortest propagation time is 1.5 to 2.0 times as large as J/sub e/ for maximum f/sub T/. This ECL array was designed for multi-gigabit system operation and, in addition to digital, logic, and analog functions, it is easily configurable to provide high-speed functions such as clock distributors, shift registers, and ripple counters.<>

Keywords

bipolar integrated circuits; elemental semiconductors; emitter-coupled logic; logic arrays; silicon; 0.3 micron; 9.5 GHz; 9.5 Gbit/s; Si; bipolar ECL array; emitter coupled logic; high-speed functions; multi-gigabit system operation; Circuit synthesis; Coupling circuits; Current density; Design optimization; Logic arrays; Logic circuits; Logic design; Logic gates; Packaging; Switching circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1992. Digest of Technical Papers. 39th ISSCC, 1992 IEEE International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-0573-6

Type

conf

DOI

10.1109/ISSCC.1992.200407

Filename

200407