Title :
Extension of inductive fault analysis to parametric faults in analog circuits with application to test generation
Author :
Jaworski, Zbigniew ; Niewczas, Mariusz ; Kuzmicz, Wieslaw
Author_Institution :
Inst. of Microelectron. & Optoelectron., Warsaw Univ. of Technol., Poland
fDate :
27 Apr-1 May 1997
Abstract :
Parametric fault modeling methodology based on statistical process simulation is proposed. Statistical simulation based on process disturbances allows one to avoid testing for faults which are unlikely to occur. As a result, the number of tests required to verify the circuit´s performance is reduced. A practical example with results measured on prototype chips is presented
Keywords :
VLSI; analogue integrated circuits; circuit analysis computing; fault diagnosis; integrated circuit testing; statistical analysis; VLSI; analog circuits; circuit performance; inductive fault analysis; parametric faults; process disturbances; statistical process simulation; test generation; Analog circuits; Circuit faults; Circuit simulation; Circuit testing; Data mining; Frequency response; Manufacturing processes; Sensitivity analysis; Tellurium; Voltage;
Conference_Titel :
VLSI Test Symposium, 1997., 15th IEEE
Conference_Location :
Monterey, CA
Print_ISBN :
0-8186-7810-0
DOI :
10.1109/VTEST.1997.600249
