Interconnect diagnosis of bus-connected multi-RAM systems

Author

Zhao, Jun ; Meyer, Fred J. ; Lombardi, Fabrizio

Author_Institution

Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA

fYear

1999

fDate

1999

Firstpage

40

Lastpage

47

Abstract

This paper presents a novel approach for detection and diagnosis (with no confounding or aliasing) of interconnect faults (short and stuck-at) in a system consisting of multiple RAM chips connected through busses. These systems (referred to as a bus-connected multi RAM systems, or BCMRS) are characterized by multiple types of lines (bus and driver lines), disjoint busses (address and data) as well as by the presence of memories (whose number is given by D). Different testing objectives (detection and maximal diagnosis) are considered. An extensive analysis of the faults is pursued to characterize their impact on the BCMRS as well as on the test operations (such as WRITE and READ)

Keywords

driver circuits; fault diagnosis; integrated circuit interconnections; integrated memory circuits; random-access storage; wiring; BCMRS; bus lines; bus-connected multi-RAM systems; disjoint busses; driver lines; interconnect diagnosis; interconnect faults; maximal diagnosis; multiple RAM chips; multiple line types; shorts; stuck-at faults; test operations; testing objectives; Computer science; Electrical fault detection; Electronic switching systems; Fault detection; Fault diagnosis; Hip; Joining processes; Random access memory; Read-write memory; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Memory Technology, Design and Testing, 1999. Records of the 1999 IEEE International Workshop on

Conference_Location

San Jose, CA

ISSN

1087-4852

Print_ISBN

0-7695-0259-8

Type

conf

DOI

10.1109/MTDT.1999.782682

Filename

782682