DocumentCode
3038559
Title
Racetrack memory cell array with integrated magnetic tunnel junction readout
Author
Annunziata, A.J. ; Gaidis, M.C. ; Thomas, L. ; Chien, C.W. ; Hung, C.C. ; Chevalier, P. ; O´Sullivan, E.J. ; Hummel, J.P. ; Joseph, E.A. ; Zhu, Y. ; Topuria, T. ; Delenia, E. ; Rice, P.M. ; Parkin, S.S.P. ; Gallagher, W.J.
Author_Institution
IBM T. J. Watson Res. Center, Yorktown Heights, NY, USA
fYear
2011
fDate
5-7 Dec. 2011
Abstract
In this paper, we report the first demonstration of CMOS-integrated racetrack memory. The devices measured are complete memory cells integrated into the back end of line of IBM 90 nm CMOS. We show good integration yield across 200 mm wafers. With magnetic field-assist, we demonstrate current-driven read and write operations on cells within a 256-cell CMOS-integrated array.
Keywords
CMOS memory circuits; magnetic tunnelling; CMOS-integrated racetrack memory; IBM CMOS line back end; current-driven read-write operations; integrated magnetic tunnel junction readout; integration yield; magnetic field-assist; racetrack memory cell array; Arrays; CMOS integrated circuits; Magnetic domain walls; Magnetic domains; Magnetic tunneling; Nanoscale devices; Resistance;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting (IEDM), 2011 IEEE International
Conference_Location
Washington, DC
ISSN
0163-1918
Print_ISBN
978-1-4577-0506-9
Electronic_ISBN
0163-1918
Type
conf
DOI
10.1109/IEDM.2011.6131604
Filename
6131604
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