Arbitrary Error Detection in Combinational Circuits by Using Partitioning

The paper presents a new technique for designing a concurrently checking combinational circuit. The technique is based on partitioning the circuit into two independent sub-circuits. It does not require any redundant coding variables; instead, it utilizes a sub-set of input variables. These variables are transferred directly into a checker providing the arbitrary error detection. The paper develops and studies a method for selecting an optimized sub-set of such variables. Benchmark results show efficiency of the proposed approach.