Performance analysis of on-chip communication architecture in MPSoC

Soc is a technology that integrates heterogeneous system components such as microprocessors, memory logic and DSP´s into a single chip. The overall performance of SoC design depends on efficient on-chip communication architectures. Efficient interconnection architecture is necessary interprocessor communication, communication between processors and peripherals and between processor and memory. The communication architecture should be flexible in such a way that it should adapt to various traffic conditions. Currently on-chip interconnection networks are mostly implemented using shared buses which are the most common medium. The arbitration plays a crucial role in determining performance of bus-based system, as it assigns priorities, with which processor is granted the access to the shared communication resources. In the conventional arbitration algorithms there are some drawbacks such as bus starvation problem and low system performance. Hence in this paper, probability based dynamically configurable Round robin arbiters are proposed to handle the discrepancy of existing arbitration algorithms. This bus provides each component a flexible and utmost share of on-chip communication bandwidth and improves the latency in access of the shared bus. The performance of SoC is improved using this probabilistic round robin algorithm with regard to the parameters, latency compared to conventional bus arbitration algorithms.