Title :
A 8 Gb/s Si bipolar phase and frequency detector IC for clock extraction
Author :
Pottbacker, A. ; Langmann, U. ; Schreiber, H.-U.
Author_Institution :
Ruhr-Univ. Bochum, Germany
Abstract :
A clock recovery (CR) approach based on a phase and frequency detector (PFD) has been implemented in a phase-and frequency-locked loop (PFLL). CR controlled by a PFD has been demonstrated up to 4 Gb/s. The Si bipolar PFD presented here operates up to 8 Gb/s, demonstrating its application in a PFLL. A block diagram is presented which shows that the input data stream samples the VCO signal and the delayed VCO signal (delay about 90 degrees ) in two sample-and-hold cells (S/H) that serve as phase detector (PD) and quadrature phase detector (QPD), respectively.<>
Keywords :
bipolar integrated circuits; phase-locked loops; variable-frequency oscillators; 8 Gbit/s; Si; VCO signal; clock extraction; delayed VCO signal; frequency detector IC; phase detector; phase-and frequency-locked loop; quadrature phase detector; sample-and-hold cells; Bipolar integrated circuits; Chromium; Clocks; Delay; Filters; Logic; Phase detection; Phase frequency detector; Phase locked loops; Voltage-controlled oscillators;
Conference_Titel :
Solid-State Circuits Conference, 1992. Digest of Technical Papers. 39th ISSCC, 1992 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-0573-6
DOI :
10.1109/ISSCC.1992.200427
