DocumentCode
3038715
Title
Efficient Determination of Fault Criticality for Manufacturing Test Set Optimization
Author
Shi, Yiwen ; DiPalma, Kellie ; Dworak, Jennifer
Author_Institution
Brown Univ., Providence, RI
fYear
2008
fDate
1-3 Oct. 2008
Firstpage
403
Lastpage
411
Abstract
Defective part levels of zero are almost impossible to achieve in an era of complex defects, process variations, and limited testing resources. It is important to ensure that any defects missed during test will impact the end user as little as possible. However, optimizing test sets for superior detection of critical defects requires an understanding of relative fault criticality, and this determination may be very expensive. In this paper, we will present a method which efficiently estimates this criticality under realistic usage conditions using a translation between combinational and sequential fault analysis. We will show that the resulting criticalities are sufficiently accurate to select an optimized test set which is as effective as one created with perfect criticality information.
Keywords
logic testing; sequential circuits; combinational fault analysis; fault criticality; sequential fault analysis; test set optimization; Automatic test pattern generation; Circuit faults; Circuit testing; Error analysis; Fault detection; Fault diagnosis; Manufacturing; Sampling methods; Sequential analysis; System testing; ELF-MD; fault criticality; simulation; test escape quality; test escapes; test quality; test set optimization;
fLanguage
English
Publisher
ieee
Conference_Titel
Defect and Fault Tolerance of VLSI Systems, 2008. DFTVS '08. IEEE International Symposium on
Conference_Location
Boston, MA
ISSN
1550-5774
Print_ISBN
978-0-7695-3365-0
Type
conf
DOI
10.1109/DFT.2008.48
Filename
4641197
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