Chip-level power-performance optimization through thermally-driven across-chip variation (ACV) reduction

Author

Yu, X. ; Gluschenkov, O. ; Zamdmer, N.D. ; Deng, J. ; Goplen, B.A. ; Landis, H.S. ; Logan, L.R. ; Culp, J.A. ; Liang, Y. ; Cai, M. ; Lee, W. ; Rovedo, N. ; Tamweber, F.D. ; Lea, D.M. ; Greene, B.J. ; Sim, J. ; Slisher, D.K. ; Chou, A.I. ; Chang, P. ; Trom

Author_Institution

Semicond. R&D Center, IBM, Hopewell Jct, NY, USA

fYear

2011

fDate

5-7 Dec. 2011

Abstract

We report a detailed study of the impact of systematic across-chip variation (ACV) on chip level power-performance. We propose a metric to capture impact of ACV on chip-level leakage quantitatively. Product power-performance can be optimized by minimizing systematic ACV. Thermally-driven ACV was identified as a major mechanism in 32nm SOI technology. An optimized thermal anneal process was used to suppress ACV significantly, leading to a dramatic benefit in leakage power-performance trade-off.

Keywords

MOSFET; annealing; elemental semiconductors; low-power electronics; silicon; silicon-on-insulator; MOSFET; SOI technology; Si; chip-level leakage quantitative; chip-level power-performance optimization; leakage power-performance trade-off; optimized thermal anneal process; size 32 nm; thermally-driven ACV reduction; thermally-driven across-chip variation reduction; Annealing; Heating; Layout; Systematics; Temperature; Temperature measurement; Temperature sensors;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting (IEDM), 2011 IEEE International

Conference_Location

Washington, DC

ISSN

0163-1918

Print_ISBN

978-1-4577-0506-9

Electronic_ISBN

0163-1918

Type

conf

DOI

10.1109/IEDM.2011.6131611

Filename

6131611