Drain current variability and MOSFET parameters correlations in planar FDSOI technology

We present for the first time an extensive experimental study of the statistical variability of the drain current (I_D) in 6nm thin undoped Silicon-On-Insulator (SOI) MOSFETs. I_D variations (σ_ID) are found to be highly correlated with both threshold voltage (V_T) and ON-state resistance (R_ON) fluctuations. Their respective contributions cannot be directly added to capture σ_ID because of an advantageous ΔV_T/ΔR_ON correlation. Taking into account such correlations is of great interest for an accurate definition of spice model corners. We also evidence the main technological sources of I_D fluctuation. Improving the access resistances (R_SD) enables to lowering the R_ON variability. Engineering of the source/drain implantations (Low temperature C+P co-implant) mainly reduces the current (I_SAT, I_OFF) variability through an improved V_T control.