New layout dependency in high-k/Metal Gate MOSFETs

Author

Hamaguchi, M. ; Nair, D. ; Jaeger, D. ; Nishimura, H. ; Li, W. ; Na, M-H ; Bernicot, C. ; Liang, J. ; Stahrenberg, K. ; Kim, K. ; Eller, M. ; Lee, K-C ; Iwamoto, T. ; Teh, Y-W ; Mori, S. ; Takasu, Y. ; Park, JH ; Song, L. ; Kim, N-S ; Kohler, S. ; Kothari

Author_Institution

Toshiba Corp., Kawasaki, Japan

fYear

2011

fDate

5-7 Dec. 2011

Abstract

We report a new N/PFET Gate Patterning Boundary Proximity layout dependent effect in high-k dielectric/Metal Gate (HK/MG) MOSFETs which causes anomalous threshold voltage (V_t) modulation for the first time. We investigated the mechanism by using special test structures and process optimizations to suppress this layout dependency. Finally, we achieved the best over all process optimization which makes it possible to suppress layout dependency without degrading FET performance/yield/reliability.

Keywords

MOSFET; high-k dielectric thin films; semiconductor device reliability; FET performance; FET reliability; FET yield; HK-MG MOSFET; N-PFET gate patterning boundary proximity layout-dependent effect; high-k dielectric metal gate MOSFET; layout dependency suppression; process optimizations; test structures; threshold voltage modulation; Layout; Lithography; Logic gates; Materials; Metals; Optimization; Proximity effect;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting (IEDM), 2011 IEEE International

Conference_Location

Washington, DC

ISSN

0163-1918

Print_ISBN

978-1-4577-0506-9

Electronic_ISBN

0163-1918

Type

conf

DOI

10.1109/IEDM.2011.6131614

Filename

6131614